# cPy - simulated shuttle 2 x 3 one wire 2-aspect signals
#    sequencing through a pattern, using library and reduce i/o time
# by Anthony Vogelaar, Perth Scotland
# rev 0.10  2024-10-30  initial release

from	machine_sim	import	Pin
import	time
from	ve_rw2050	import	portA

# =========================== Hardware set-up =============================

RED   = 0
GREEN = 1

signals   = [Pin(pin_nr, Pin.OUT, value=RED) for pin_nr in portA]
patterns  = ((1, 1, 1, 0, 0, 0), (0, 1, 1, 0, 0, 0), (0, 0, 1, 0, 0, 0), (0, 0, 0, 0, 0, 0),
             (0, 0, 0, 1, 1, 1), (0, 0, 0, 0, 1, 1), (0, 0, 0, 0, 0, 1), (0, 0, 0, 0, 0, 0))
ptrn_last = (0, 0, 0, 0, 0, 0)

# ============================= local ===========================

# delay for dly seconds, print '*' @ 1 Hz and background task @ 10 Hz
def delay(dly):
    for tSec in range(dly):
        for t100mS in range(10):
            Pin.qtExe()						# background task - GPIO simulator
            time.sleep(0.1)
        print('*', end='', flush=True)


# set 6 signals according pattern
def setPattern(pattern):
    global ptrn_last
    
    for signal, aspect, aspect_last in zip(signals, pattern, ptrn_last):
        if aspect_last != aspect:
            signal.value(aspect)    
            print(signal, aspect)
    ptrn_last = pattern
            
# ============================== main =====================================

# cycle through shuttle patterns
def main():
    while True:
        for pattern in patterns:
            print(pattern)
            setPattern(pattern)
            delay(2)
            if pattern == (0, 0, 0, 0, 0, 0):	# if train in A or B
                print('reverse')
                delay(3)
        

main()

# ================================= End =====================================

